1. Field of the Invention
The present invention is related to a phase lock loop (“PLL”) frequency synthesizer. More specifically, the present invention is related to a PLL frequency synthesizer having a phase rotator inside the PLL loop to provide fine frequency control.
2. Background Art
Conventional systems use frequency synthesizers to generate new clock frequency based on a reference frequency clock. Some examples of such frequency synthesizers are Fractional-N type phase lock loop (“PLL”) circuit or Direct Digital Frequency Synthesizer (“DDFS”) type PLL. These systems have several disadvantages. For instance, Fractional-N type PLL systems have complicated digital modulation scheme and poor spur noise. On the other hand, DDFS type PLL systems require a read-only memory (“ROM”) table and a digital-to-analog converter (“DAC”), which consume a lot of power and circuit area. Therefore, there is a need for a better frequency synthesizer with improved PLL architecture that is capable of reducing jitter in the system without compromising power and/or circuit area.